
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
76
M9999-100207-1.5
Bit
Default
R/W
Description
2 – 0
111
RW
Port VLAN membership
Define the port’s Port VLAN membership. Bit 2 stands for the host port,
bit 1 for port 2, and bit 0 for port 1. The Port can only communicate within
the membership. An ‘1’ includes a port in the membership; an ‘0’
excludes a port from the membership.
Port 1 VID Control Register (Offset 0x0504): P1VIDCR
This register contains the global per port control for the switch port 1 function.
Bit
Default
R/W
Description
15-13
000
RW
User Priority bits
Port 1 tag [15-13] for priority
12
0
RW
CFI bit
Port 1 tag [12] for CFI
11-0
0x001
RW
VID
Port 1 tag [11-0] for VID
Note: P1VIDCR serve two purposes:
(1) Associated with the ingress untagged packets, and used for egress tagging.
(2) Default VID for the ingress untagged or null-VID-tagged packets, and used for address look up.
Port 1 Control Register 3 (Offset 0x0506): P1CR3
This register contains the port 1 control register for the switch port 1 function.
Bit
Default
R/W
Description
15 – 5
00000000000
RO
Reserved
4
0
RW
Reserved
3:2
00
RW
Ingress Limit Mode.
These bits determine what kinds of frames are limited and counted
against Ingress limiting as follows:
00 = limit and count all frames
01 = limit and count Broadcast, Multicast, and flooded unicast frames
10 = limit and count Broadcast and Multicast frames only
11 = limit and count Broadcast frames only
1
0
RW
Count IFG bytes
1 = each frame’s minimum inter frame gap
(IFG) bytes (12 per frame) are included in Ingress and Egress rate
limiting calculations.
0 = IFG bytes are not counted
0
RW
Count Preamble bytes
1 = each frame’s preamble bytes (8 per frame) are included in Ingress
and Egress rate limiting calculations.
0 = preamble bytes are not counted